DRA821U-Q1 Series

Automotive gateway SoC with dual Arm® Cortex®-A72, quad Cortex-R5F, four-port Ethernet switch, PCIe

Catalog

Automotive gateway SoC with dual Arm® Cortex®-A72, quad Cortex-R5F, four-port Ethernet switch, PCIe

Part	Speed	Speed	Supplier Device Package	Peripherals	Operating Temperature [Min]	Operating Temperature [Max]	Architecture	RAM Size	Core Processor	Package / Case	Qualification	Grade	Connectivity	Number of I/O
Texas Instruments DRA821U4TCBALMRQ1	2 GHz	1 GHz	433-FCBGA (17.2x17.2)	DMA PWM WDT	-40 °C	125 ¯C	MCU MPU	1.5 MB	ARM® Cortex®-A72 ARM® Cortex®-R5F	433-BFBGA FCBGA	AEC-Q100	Automotive	Ethernet I2C I3C MCAN MMC/SD/SDIO SPI UART USB	141

Catalog

Automotive gateway SoC with dual Arm® Cortex®-A72, quad Cortex-R5F, four-port Ethernet switch, PCIe

Key Features

• Processor cores:Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS1MB L2 shared cache per dual-core Cortex-A72 cluster32KB L1 DCache and 48KB L1 ICache per A72 core4× Arm Cortex-R5F MCUs at up to 1.0 GHz with optional lockstep operation, 8K DMIPS32K I-Cache, 32K D-Cache, 64K L2 TCM2× Arm Cortex-R5F MCUs in isolated MCU subsystem2× Arm Cortex-R5F MCUs in general compute partitionMemory subsystem:1MB of On-Chip L3 RAM with ECC and coherencyECC error protectionShared coherent cacheSupports internal DMA engineExternal Memory Interface (EMIF) module with ECCSupports LPDDR4 memory types that comply with the JESD209-4B specification. (No support for byte mode LPDDR4 memories, or memories with more than 17 row address bits)Supports speeds up to 3200 MT/s32-bit and 16-bit data bus with inline ECC bus up to 12.8GB/sGeneral-Purpose Memory Controller (GPMC)512KB on-chip SRAM in MAIN domain, protected by ECCVirtualization:Hypervisor support in Arm Cortex-A72Independent processing subsystems with Arm Cortex-A72, Arm Cortex-R5F with isolated safety MCU islandIO virtualization supportPeripheral Virtualization Unit (PVU) for low latency high bandwidth peripheral trafficMulti-region firewall support for memory and peripheral isolationVirtualization support with Ethernet, PCIe, and DMADevice security (on select part numbers):Secure boot with secure runtime supportCustomer programmable root key, up to RSA-4K or ECC-512Embedded hardware security moduleCrypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DESFunctional Safety:Functional Safety-Complianttargeted (on select part numbers)Developed for functional safety applicationsDocumentation will be available to aid ISO 26262 and IEC 61508 functional safety system design up to ASIL-D/SIL-3 targetedSystematic capability up to ASIL-D/SIL-3 targetedHardware integrity up to ASIL-D/SIL-3 targeted for MCU DomainHardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main DomainHardware integrity up to ASIL-B/SIL-2 targeted for remainder of the Main DomainFFI isolation provided between EMCU and the remainder of the Main DomainSafety-related certificationISO 26262 and IEC 61508 plannedAEC-Q100 qualified on part number variants ending in Q1High-speed interfaces:Integrated Ethernet TSN/AVB switch supporting up to 4 (DRA821U4) or 2 (DRA821U2) external ports:One port supports 5Gb, 10Gb USXGMII/XFIAll ports support 2.5Gb SGMIIAll ports support 1Gb SGMII/RGMIIDRA821U4: Any single port can support QSGMII (using all 4 internal ports)Non-blocking wire-rate store and forward switchInterVLAN (Layer3) routing supportTime synchronization support with IEEE 1588(annex D,E,F)TSN/AVB support for traffic scheduling, shapingPort mirroring feature for debug and diagnosticsPolicing and rate limiting supportOne RGMII/RMII port in safety MCU islandOne PCI-Express Gen3 controllerGen1, Gen2, and Gen3 operation with auto-negotiation4× lanesOne USB 3.1 Gen1 dual-role device subsystemSupports type-C switchingIndependently configurable as USB host, USB peripheral, or USB dual-role deviceAutomotive interfaces:Twenty CAN-FD ports12× Universal Asynchronous Receiver/Transmitter (UART)11× Serial Peripheral Interfaces (SPI)One 8-channel ADC10× Inter-Integrated Circuit ( I2C™)2× Improved Inter-Integrated Circuit ( I3C)Audio interfaces:3× Multichannel Audio Serial Port (McASP) modulesFlash memory interfaces:Embedded Multi Media Card ( eMMC™ 5.1) interfaceSupport speeds of up to HS400One Secure Digital 3.0/Secure Digital Input Output 3.0 (SD3.0/SDIO3.0) interfacesOne Octal SPI / Xccela™ / HyperBus™ Memory Controller (HBMC) interface16-nm FinFET technology17.2 mm x 17.2 mm, 0.8 mm pitch, IPC Class 3 PCBProcessor cores:Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS1MB L2 shared cache per dual-core Cortex-A72 cluster32KB L1 DCache and 48KB L1 ICache per A72 core4× Arm Cortex-R5F MCUs at up to 1.0 GHz with optional lockstep operation, 8K DMIPS32K I-Cache, 32K D-Cache, 64K L2 TCM2× Arm Cortex-R5F MCUs in isolated MCU subsystem2× Arm Cortex-R5F MCUs in general compute partitionMemory subsystem:1MB of On-Chip L3 RAM with ECC and coherencyECC error protectionShared coherent cacheSupports internal DMA engineExternal Memory Interface (EMIF) module with ECCSupports LPDDR4 memory types that comply with the JESD209-4B specification. (No support for byte mode LPDDR4 memories, or memories with more than 17 row address bits)Supports speeds up to 3200 MT/s32-bit and 16-bit data bus with inline ECC bus up to 12.8GB/sGeneral-Purpose Memory Controller (GPMC)512KB on-chip SRAM in MAIN domain, protected by ECCVirtualization:Hypervisor support in Arm Cortex-A72Independent processing subsystems with Arm Cortex-A72, Arm Cortex-R5F with isolated safety MCU islandIO virtualization supportPeripheral Virtualization Unit (PVU) for low latency high bandwidth peripheral trafficMulti-region firewall support for memory and peripheral isolationVirtualization support with Ethernet, PCIe, and DMADevice security (on select part numbers):Secure boot with secure runtime supportCustomer programmable root key, up to RSA-4K or ECC-512Embedded hardware security moduleCrypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DESFunctional Safety:Functional Safety-Complianttargeted (on select part numbers)Developed for functional safety applicationsDocumentation will be available to aid ISO 26262 and IEC 61508 functional safety system design up to ASIL-D/SIL-3 targetedSystematic capability up to ASIL-D/SIL-3 targetedHardware integrity up to ASIL-D/SIL-3 targeted for MCU DomainHardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main DomainHardware integrity up to ASIL-B/SIL-2 targeted for remainder of the Main DomainFFI isolation provided between EMCU and the remainder of the Main DomainSafety-related certificationISO 26262 and IEC 61508 plannedAEC-Q100 qualified on part number variants ending in Q1High-speed interfaces:Integrated Ethernet TSN/AVB switch supporting up to 4 (DRA821U4) or 2 (DRA821U2) external ports:One port supports 5Gb, 10Gb USXGMII/XFIAll ports support 2.5Gb SGMIIAll ports support 1Gb SGMII/RGMIIDRA821U4: Any single port can support QSGMII (using all 4 internal ports)Non-blocking wire-rate store and forward switchInterVLAN (Layer3) routing supportTime synchronization support with IEEE 1588(annex D,E,F)TSN/AVB support for traffic scheduling, shapingPort mirroring feature for debug and diagnosticsPolicing and rate limiting supportOne RGMII/RMII port in safety MCU islandOne PCI-Express Gen3 controllerGen1, Gen2, and Gen3 operation with auto-negotiation4× lanesOne USB 3.1 Gen1 dual-role device subsystemSupports type-C switchingIndependently configurable as USB host, USB peripheral, or USB dual-role deviceAutomotive interfaces:Twenty CAN-FD ports12× Universal Asynchronous Receiver/Transmitter (UART)11× Serial Peripheral Interfaces (SPI)One 8-channel ADC10× Inter-Integrated Circuit ( I2C™)2× Improved Inter-Integrated Circuit ( I3C)Audio interfaces:3× Multichannel Audio Serial Port (McASP) modulesFlash memory interfaces:Embedded Multi Media Card ( eMMC™ 5.1) interfaceSupport speeds of up to HS400One Secure Digital 3.0/Secure Digital Input Output 3.0 (SD3.0/SDIO3.0) interfacesOne Octal SPI / Xccela™ / HyperBus™ Memory Controller (HBMC) interface16-nm FinFET technology17.2 mm x 17.2 mm, 0.8 mm pitch, IPC Class 3 PCB

Description

Jacinto™ DRA821x processors, based on the Armv8 64-bit architecture, are optimized for gateway systems with cloud connectivity. The System-on-Chip (SoC) design reduces system-level costs and complexity through integration—notably, a system MCU, functional safety and security features, and an Ethernet switch for high-speed communication. Integrated diagnostics and functional safety features are targeted to ASIL-D and SIL 3 certification requirements. Real-time control and low-latency communication are enabled by a PCIe controller and a TSN capable Gigabit Ethernet switch. Up to four general-purpose Arm® Cortex®-R5F subsystems can handle low-level, timing-critical processing tasks and leave the Arm® Cortex®-A72 core unencumbered for advanced and cloud-based applications. Jacinto DRA821x processors also include the concept of the Extended MCU (eMCU) domain. This domain is a subset of the processors and peripherals on the main domain targeted at higher functional safety enablement, such as ASIL-D/SIL-3. The functional block diagram highlights which IP are included in the eMCU. For more details about eMCU and functional safety, see the DRA821 Safety Manual Processors Texas Instruments Jacinto™ 7 Family of Products (SPRUIX4). Jacinto™ DRA821x processors, based on the Armv8 64-bit architecture, are optimized for gateway systems with cloud connectivity. The System-on-Chip (SoC) design reduces system-level costs and complexity through integration—notably, a system MCU, functional safety and security features, and an Ethernet switch for high-speed communication. Integrated diagnostics and functional safety features are targeted to ASIL-D and SIL 3 certification requirements. Real-time control and low-latency communication are enabled by a PCIe controller and a TSN capable Gigabit Ethernet switch. Up to four general-purpose Arm® Cortex®-R5F subsystems can handle low-level, timing-critical processing tasks and leave the Arm® Cortex®-A72 core unencumbered for advanced and cloud-based applications. Jacinto DRA821x processors also include the concept of the Extended MCU (eMCU) domain. This domain is a subset of the processors and peripherals on the main domain targeted at higher functional safety enablement, such as ASIL-D/SIL-3. The functional block diagram highlights which IP are included in the eMCU. For more details about eMCU and functional safety, see the DRA821 Safety Manual Processors Texas Instruments Jacinto™ 7 Family of Products (SPRUIX4).