LMK1D2106 Series

Dual bank 6-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer

Catalog

Dual bank 6-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer

Part	Operating Temperature [Max]	Operating Temperature [Min]	Differential - Input:Output [custom]	Differential - Input:Output [custom]	Mounting Type	Input	Ratio - Input:Output [custom]	Ratio - Input:Output [custom]	Package / Case	Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Number of Circuits	Output	Frequency - Max [Max]	Supplier Device Package
Texas Instruments LMK1D2106RHAR	105 °C	-40 °C			Surface Mount	CML HCSL LVCMOS LVDS LVPECL	6	2	40-VFQFN Exposed Pad	Clock Buffer	1.71 V 2.375 V 3.135 V	1.89 V 2.625 V 3.465 V	2	Clock LVDS	2 GHz	40-VQFN (6x6)
Texas Instruments LMK1D2106RHAT	105 °C	-40 °C			Surface Mount	CML HCSL LVCMOS LVDS LVPECL	6	2	40-VFQFN Exposed Pad	Clock Buffer	1.71 V 2.375 V 3.135 V	1.89 V 2.625 V 3.465 V	2	Clock LVDS	2 GHz	40-VQFN (6x6)

Catalog

Dual bank 6-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer

Key Features

• High-performance LVDS clock buffer family: up to 2 GHzDual 1:6 differential bufferDual 1:8 differential bufferSupply voltage: 1.71 V to 3.465 VLow additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHzVery low phase noise floor: -164 dBc/Hz (typical)Very low propagation delay: < 575 ps maximumOutput skew: 20 ps maximumHigh-swing LVDS (boosted mode): 500-mV VOD typical when AMP_SEL = 1Bank enable/disable using the EN pinFail-safe input operationUniversal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levelsLVDS reference voltage, VAC_REF, available for capacitive-coupled inputsIndustrial temperature range: –40°C to 105°CPackaged inLMK1D2106: 6-mm × 6-mm, 40-pin VQFN (RHA)LMK1D2108: 7-mm × 7-mm, 48-pin VQFN (RGZ)High-performance LVDS clock buffer family: up to 2 GHzDual 1:6 differential bufferDual 1:8 differential bufferSupply voltage: 1.71 V to 3.465 VLow additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHzVery low phase noise floor: -164 dBc/Hz (typical)Very low propagation delay: < 575 ps maximumOutput skew: 20 ps maximumHigh-swing LVDS (boosted mode): 500-mV VOD typical when AMP_SEL = 1Bank enable/disable using the EN pinFail-safe input operationUniversal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levelsLVDS reference voltage, VAC_REF, available for capacitive-coupled inputsIndustrial temperature range: –40°C to 105°CPackaged inLMK1D2106: 6-mm × 6-mm, 40-pin VQFN (RHA)LMK1D2108: 7-mm × 7-mm, 48-pin VQFN (RGZ)

Description

The LMK1D210x clock buffer distributes two clock inputs (IN0 and IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0 to OUT15) in the LMK1D2108 and 12 pairs of clock outputs (OUT0 to OUT11) in the LMK1D2106 with minimum skew for clock distribution. Each buffer block consists of one input and a maximum of 6 (LMK1D2106) or 8 (LMK1D2108) LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML, or LVCMOS. The LMK1D210x is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin (see Figure 8-6). Using the control pin (EN), output banks can either be enable or disabled. If this pin is left open, both bank outputs are enabled. If the control pin is switched to a logic "0", both bank outputs are disabled (static logic "0"). If the control pin is switched to a logic "1", the outputs of one bank are disabled while the outputs of the other bank are enabled. The part also supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal. The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature). The LMK1D210x clock buffer distributes two clock inputs (IN0 and IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0 to OUT15) in the LMK1D2108 and 12 pairs of clock outputs (OUT0 to OUT11) in the LMK1D2106 with minimum skew for clock distribution. Each buffer block consists of one input and a maximum of 6 (LMK1D2106) or 8 (LMK1D2108) LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML, or LVCMOS. The LMK1D210x is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin (see Figure 8-6). Using the control pin (EN), output banks can either be enable or disabled. If this pin is left open, both bank outputs are enabled. If the control pin is switched to a logic "0", both bank outputs are disabled (static logic "0"). If the control pin is switched to a logic "1", the outputs of one bank are disabled while the outputs of the other bank are enabled. The part also supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal. The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).