LMK01801 Series

Dual clock distribution

Catalog

Dual clock distribution

Part	Operating Temperature [Max]	Operating Temperature [Min]	Voltage - Supply [Max]	Voltage - Supply [Min]	Output	Number of Circuits	Type	Ratio - Input:Output [custom]	Mounting Type	Supplier Device Package	Package / Case	Frequency - Max [Max]	Input
Texas Instruments LMK01801BISQX/NOPB	85 °C	-40 °C	3.45 V	3.15 V	LVCMOS LVDS LVPECL	2	Divider Fanout Buffer (Distribution) Multiplexer	1:6 1:8	Surface Mount	48-WQFN (7x7)	48-WFQFN Exposed Pad	3.1 GHz	LVCMOS LVDS LVPECL RF Sinewave
Texas Instruments LMK01801BISQ/NOPB	85 °C	-40 °C	3.45 V	3.15 V	LVCMOS LVDS LVPECL	2	Divider Fanout Buffer (Distribution) Multiplexer	1:6 1:8	Surface Mount	48-WQFN (7x7)	48-WFQFN Exposed Pad	3.1 GHz	LVCMOS LVDS LVPECL RF Sinewave
Texas Instruments LMK01801BISQE/NOPB	85 °C	-40 °C	3.45 V	3.15 V	LVCMOS LVDS LVPECL	2	Divider Fanout Buffer (Distribution) Multiplexer	1:6 1:8	Surface Mount	48-WQFN (7x7)	48-WFQFN Exposed Pad	3.1 GHz	LVCMOS LVDS LVPECL RF Sinewave

Catalog

Dual clock distribution

Key Features

• Pin control mode or MICROWIRE (SPI)Input and output frequency range: 1 kHz to 3.1 GHzSeparate input for clock output banks A and B14 differential clock outputs in two banks (A and B)Output Bank A8 differential, programmable outputs (up to 8 as LVCMOS)Divider values of 1 to 8, even and odd.Output Bank B6 differential outputs (or up to 12 as LVCMOS)Divides values of 1 to 1045 or 1 to 8, even and oddAnalog and digital delays50% duty cycle on all outputs for all dividesSeparate synchronization of bank A and B.RMS additive jitter 50 fs at 800 MHz50-fs RMS additive jitter (12 kHz to 20 MHz)Industrial temperature range: –40°C to 85°C3.15-V to 3.45-V OperationPin control mode or MICROWIRE (SPI)Input and output frequency range: 1 kHz to 3.1 GHzSeparate input for clock output banks A and B14 differential clock outputs in two banks (A and B)Output Bank A8 differential, programmable outputs (up to 8 as LVCMOS)Divider values of 1 to 8, even and odd.Output Bank B6 differential outputs (or up to 12 as LVCMOS)Divides values of 1 to 1045 or 1 to 8, even and oddAnalog and digital delays50% duty cycle on all outputs for all dividesSeparate synchronization of bank A and B.RMS additive jitter 50 fs at 800 MHz50-fs RMS additive jitter (12 kHz to 20 MHz)Industrial temperature range: –40°C to 85°C3.15-V to 3.45-V Operation

Description

The LMK01801 is a very low noise solution for clocking systems that require distribution and frequency division of precision clocks. The LMK01801 features extremely low residual noise, frequency division, digital and analog delay adjustments, and fourteen (14) programmable differential outputs: LVPECL, LVDS and LVCMOS (2 outputs per differential output). The LMK01801 features two independent inputs that can be driven differentially (LVDS, LVPECL) or in single-ended mode (LVCMOS, RF Sinewave). The first input drives output Bank A consisting of eight (8) outputs. The second input drives output Bank B consisting of six (6) outputs. The LMK01801 is a very low noise solution for clocking systems that require distribution and frequency division of precision clocks. The LMK01801 features extremely low residual noise, frequency division, digital and analog delay adjustments, and fourteen (14) programmable differential outputs: LVPECL, LVDS and LVCMOS (2 outputs per differential output). The LMK01801 features two independent inputs that can be driven differentially (LVDS, LVPECL) or in single-ended mode (LVCMOS, RF Sinewave). The first input drives output Bank A consisting of eight (8) outputs. The second input drives output Bank B consisting of six (6) outputs.