Catalog
1.5-Gbps LVDS/LVPECL/CML-to-CML translator/repeater
Key Features
• Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CMLSignaling Rates1up to 1.5 GbpsCML Compatible Output Directly Drives Devices With 3.3-V, 2.5-V, or 1.8-V SuppliesTotal Jitter < 70 psLow 100 ps (Max) Part-To-Part SkewWide Common-Mode Receiver Capability Allows Direct Coupling of Input Signals25 mV of Receiver Input Threshold Hysteresis Over 0-V to 4-V Common-Mode RangePropagation Delay Times, 800 ps Maximum3.3-V Supply OperationAvailable in SOIC and MSOP PackagesAPPLICATIONSLevel Translation622-MHz Central Office Clock DistributionHigh-Speed Network RoutingWireless BasestationsLow Jitter Clock Repeater1The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CMLSignaling Rates1up to 1.5 GbpsCML Compatible Output Directly Drives Devices With 3.3-V, 2.5-V, or 1.8-V SuppliesTotal Jitter < 70 psLow 100 ps (Max) Part-To-Part SkewWide Common-Mode Receiver Capability Allows Direct Coupling of Input Signals25 mV of Receiver Input Threshold Hysteresis Over 0-V to 4-V Common-Mode RangePropagation Delay Times, 800 ps Maximum3.3-V Supply OperationAvailable in SOIC and MSOP PackagesAPPLICATIONSLevel Translation622-MHz Central Office Clock DistributionHigh-Speed Network RoutingWireless BasestationsLow Jitter Clock Repeater1The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
Description
AI
This high-speed translator/repeater is designed for signaling rates up to 1.5 Gbps to support various high-speed network routing applications. The driver output is compatible with current-mode logic (CML) levels, and directly drives 50-loads connected to 1.8-V, 2.5-V, or 3.3-V nominal supplies. The capability for direct connection to the loads may eliminate the need for coupling capacitors. The receiver input is compatible with LVDS (TIA/EIA–644), LVPECL, and CML signaling levels. The receiver tolerates a wide common-mode voltage range, and may also be directly coupled to the signal source. The internal data path from input to output is fully differential for low noise generation and low pulse-width distortion.
The VBBpin is an internally generated voltage supply to allow operation with a single-ended LVPECL input. For single-ended LVPECL input operation, the unused differential input is connected to VBBas a switching reference voltage. When used, decouple VBBwith a 0.01-uF capacitor and limit the current sourcing or sinking to 400 uA. When not used, VBBshould be left open.
This device is characterized for operation from –40°C to 85°C.
This high-speed translator/repeater is designed for signaling rates up to 1.5 Gbps to support various high-speed network routing applications. The driver output is compatible with current-mode logic (CML) levels, and directly drives 50-loads connected to 1.8-V, 2.5-V, or 3.3-V nominal supplies. The capability for direct connection to the loads may eliminate the need for coupling capacitors. The receiver input is compatible with LVDS (TIA/EIA–644), LVPECL, and CML signaling levels. The receiver tolerates a wide common-mode voltage range, and may also be directly coupled to the signal source. The internal data path from input to output is fully differential for low noise generation and low pulse-width distortion.
The VBBpin is an internally generated voltage supply to allow operation with a single-ended LVPECL input. For single-ended LVPECL input operation, the unused differential input is connected to VBBas a switching reference voltage. When used, decouple VBBwith a 0.01-uF capacitor and limit the current sourcing or sinking to 400 uA. When not used, VBBshould be left open.
This device is characterized for operation from –40°C to 85°C.
