/ 0
100%
74SSTUB32868ZRHRActive
Texas Instruments
28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST
Ask questions about this document, request analysis, or get help understanding technical specifications.
28-Bit to 56-Bit Registered Buffer with Address-Parity Test datasheet (Rev. C)
DDR2 Memory Interface Clocks and Registers - Overview