resistor (REXT) and capacitor (CEXT).

Once triggered, the basic output pulse width may be extended by retriggering the gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made as long as desired. Alternatively an output delay can be terminated at any time by a LOW-going edge on input nRD, which also inhibits the triggering.

An internal connection from nRD to the input gate makes it possible to trigger the circuit by a positive-going signal at input nRD. The basic output pulse width is essentially determined by the value of the external timing components REXT and CEXT. When CEXT = 10 nF, the typical output pulse width is defined as: tW= REXT× CEXT where tW= pulse width in ns; REXT= external resistor in kO; CEXT= external capacitor in pF. Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and fall times.

All inputs have a Schmitt-trigger action
Inputs accept voltages higher than V_CC
DC triggered from active HIGH or active LOW inputs
Retriggerable for very long pulses up to 100 % duty factor
Direct reset terminates output pulse
For 74AHC123A only: operates with CMOS input levels
For 74AHCT123A only: operates with TTL input levels
ESD protection:
- HBM JESD22-A114E exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
- CDM JESD22-C101C exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C

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